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ADV7391 in PAL square pixel mode issue

Question asked by Patrick_B Employee on Oct 31, 2014
Latest reply on Dec 4, 2014 by jbf

 

Ddesigning the ADV7391 and using it according the table 1 on D/S Page 5, the sixth format with a Clkin of 29.5MHz with square pixels.

 

mode « PAL Square Pixel » (768*576 points, 25 Hz image frequency and 29.5 Mhz video frequency.

 

The configuration is as described on page 96, all other registers are set up at their default values but reg0x00 = 0x10.

 

With these settings, the ADV7391 is not properly synchronized.

 

Is the HSYNC required along with the EAV/SAV markers ? Is there other thing to do ?

 

Currently, HSYNC>/VSYNC are set up to a logic 1

 

 

 

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