I wish to know that why PLL is not getting locked, Here i described my configuration and settings.
Required freq: 1091.2 MHz
Reference freq: 26 MHz
PFD Freq: 26 MHz
Feedback signal: Divided
I am programming with above settings and configuration and i am getting a signal at around 983 MHz with out locking and i tried by changing some configuration like PFD Freq as 13 MHz and small things, But i am not successful.
After i measured how much Vtune voltage was generating, i observed as 2.5 V and it is constant for over all different frequencies.
i fed external V Tune voltage eventhough output frequency is same and it is remains same when i increase to further from 0 to 2.2 V. At this moment i observed constant 1.1 V at Vtune voltage when i removed charge pump out connection, is it any device problem or it is default value?
Please help me to solve this issue and i attached my block schematic for reference.