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BF707 HRM documentation says dual cores; isn't that wrong?

Question asked by pinaz on Oct 27, 2014
Latest reply on Oct 28, 2014 by AkashA

In the ADSP-BF70x Blackfin+ Processor Hardware Reference, chapter 37 "System Debug and Trace Unit (DBG)" has a section entitled "Embedded Cross Trigger".  In it, it says things like:


"ECT provides a mechanism for multiple microprocessor based subsystems to send and receive debug triggers to and from each other."


"The main function of the ECT (CTI and CTM) is to pass debug events from one core to another. For example, the ECT can communicate debug state information from one core to another, so that program execution on both processors can be stopped at the same time if required.


The BF60x series is a dual core architecture, but has a completely different debug interface, so it seems unlikely this is a copy-and-paste mistake.


Another reference to dual cores is in Chapter 10 "L2 M EMORY CONTROLLER (L2CTL)", which says "If two cores simultaneously try to access L2 for the same kind of access (both read or both write), even to different banks, only one core access is allowed at a time, as there is only one read port and one write port shared between the cores. However, if one core issues a write and the other issues a read, then access can proceed simultaneously"


What are these dual cores being referred to?