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question about ADV7125 mininal input clock pulse width @ 165MHz input freq

Question asked by WilliamLian Employee on Oct 26, 2014
Latest reply on Nov 3, 2014 by WilliamLian

the ADV7125 datasheet, about the clock pulse width, defined as below table By the table, we can get below information, when fclk_max=140MHz, the minial clock pulse width is 2.85ns, when fclk_max=240MHz, the minial clock pulse width is 1.875ns,  in customer application, the fclk_max is 165MHz,  they want to know at the 165MHz, what's the requirment on minimal clock pulse width value? in another word, do you think 2.85ns is OK for 165MHz application?



BTW, customer said their clock pulse width is bigger than 1.875ns and smaller than 2.85ns. ADV7625 clock pulse width.png