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Charc ADSP-21489 boot problem

Question asked by ipbatman on Oct 25, 2014
Latest reply on Nov 10, 2014 by Jithul_Janardhanan

Introduction: processors BlackFin (ADSP-BF533SBSTZ400 firm Analog Devices) and Sharc (ADSP-21489BSWZ-4B firm Analog Devices) are loaded by SPI with FPGA (XC6SLX150T-3FG676I firm Xilinx). FPGA provides access to the ROM (RC28F256J3F95 firm Micron) these processors through. (scheme.jpg)

 

Scheme of work: the first is configured FPGA, in this time of the processors in reset. After loading the FPGA output from the reset state BlackFin and starts loading the data for this processor from the allocated space in the ROM (Sharc in reset). BlackFin master, FPGA slave. After downloading BlackFin Shark likewise starts loading the program from ROM. Sharc master, FPGA slave.

 

The problem with the Sharc: after reading 1536 + 5 words, the transmission stops. No CLK, but CS is set to "0" and further that does not happen. (end.jpg)

 

Program on Charc is test, simply switches the pin general purpose. (Sharc_setting_and_code.jpg)

 

Boot problems BlackFin not. (BlackFin_setting.jpg)

 

Shows oscillograms Sharc (ChipScope Pro Analyser v.14.2 P.28xd) start booting and the beginning LDR file. (start.jpg)

 

I understand the kernel is booted, but then continue the download does not go. Why? Help Board.

 

P.S. Sorry for my English

 

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