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AD7689 eval board EVAL-CN0254-SDPZ layout

Question asked by Jon_B on Oct 23, 2014
Latest reply on Oct 24, 2014 by Jon_B



I was looking at the layout for this eval board and noticed something about the decoupling on the supply pins (1 & 20).

Pin 1 goes to a 100nF and 10uF then a via to the supply rail.

Pin 20 goes to just a 100nF then a via to supply rail.

Even though the pins are adjacent, they are not tied directly together.


The datasheet just says these pins should be decoupled with 100nF and 10uF capcitors, but doesn't say if that means a pair of caps for each pin, or whether it's OK to join them together and just use one pair of caps (which is how I would assume to do it, seeing as the pins are adjacent at the corner of the package).


Is there any particular reasoning behind why these pins are decoupled the way they are on the eval board? Will performance be better with separate decoupling on these pins?