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ADAU1452 Throughput Delay

Question asked by PeterTheRed on Oct 22, 2014
Latest reply on Oct 23, 2014 by JohnTo



I'm hoping to find some information on the expected delay from an I2S Input to output of the ADAU1452 Sigma DSP configured for:


MCLK = 24.576MHz,

PLL divider settings to produce a 294.912MHz system clock,

Audio Fs = 96kHz, BCK = 3.072MHz, I2S (2-ch) format.

no sample rate conversions,

Input and output ports slaved from the same clock signals,

No audio processing, just input straight to output


...So, basically just the minimum 'baseline' latency through the serial input port, dsp core, and output port.  Some colleagues in the lab have measured something longer than expected, and since the datasheet is quiet on the subject, we're unsure if its behaving as expected or not. 


As a corollary, could the latency vary between different input and output ports, or (assuming synchronous clocks), or are the data paths guaranteed synchronous as well (processing notwithstanding)?