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AD7960 : data set up / hold times in ref design

Question asked by andrewm on Oct 22, 2014
Latest reply on Oct 22, 2014 by maithil

In the docs for the AD7960 , is a set of Verilog / Xilinx reference files for how to interface to the AD7960.




Looking at the echoed clock version, as it seems the easiest, I can not see any timing constraints for the design.


It could be they are there, but I'd expect a UCF file for ISE, or an XDC file for vivado.


I run the design in simulation , and it runs, but the timing is 'ambiguous' .


Does anyone have a the numbers to type into Xilinx tools to ensure the AD7960 interface will work,