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Questions about ADV7625 clock,  the minimal pulse width@fmax=165MHz

Question asked by WilliamLian Employee on Oct 20, 2014
Latest reply on Oct 26, 2014 by WilliamLian


the ADV7635 datasheet, about the clock pulse width, defined as below table

ADV7125 clock period.png

 

By the table, we can get below information, when fclk_max=140MHz, the minial clock pulse width is 2.85ns, when fclk_max=240MHz, the minial clock pulse width is 1.875ns,  in customer application, the fclk_max is 165MHz,  they want to know at the 165MHz, what's teh requirment on minimal clock pulse width value? BTW, customer said their clock pulse width is bigger than 1.875ns.

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