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AD9548 and AD9523-1 chain (FMCOMMS1)

Question asked by ehsantelecom on Oct 20, 2014
Latest reply on Oct 21, 2014 by Kyle.Slightom

Hello experts,

I have create another discussion in "FPGA Reference Design" but I feel here is the better place to put such the question.

 

I am working with AD-FMCOMMS1 design which you can see the block diagram here AD-FMCOMMS1-EBZ Functional Overview    [Analog Devices Wiki] . A 30MHz clock comes from FPGA board to AD9548 and the clock generated by AD9548 enters into AD9523. In this case is 30.72MHz (122.88MHz/4). This reference design works well with 122.88MHz crystal but I replace it with a 80MHz to have precise fractions. I try to generate 20MHz (80MHz/4) clock in the first stage. It seems the 20MHz is OK but the PLL1 of AD9523-1 is unlocked and PLL2 is locked ... I am not sure if it is because the input 20MHz signal generated by AD9548 or something inside AD9523-1.

 

In summary, this is the parameter I chose for profile0 in the Excel file of AD9548 evaluation software (http://www.analog.com/static/imported-files/eval_boards/AD9547_AD9548_Evaluation_Installation.zip) to adjust the parameters:

     System Clock: 768MHz

     Nominal Reference Period: 30MHz

     R: 125

     S: 335

     U: 0

     V: 1

And I kept the rest as default... Profile0 will be (reference config file no-OS/AD9548_cfg.h at master · analogdevicesinc/no-OS · GitHub):

 

        {0x0600, 0x00},

        {0x0601, 0x55},

        {0x0602, 0xA0},

        {0x0603, 0xFC},

        {0x0604, 0x01},

        {0x0605, 0x00},

        {0x0606, 0x00},

        {0x0607, 0x00},

        {0x0608, 0xE8},

        {0x0609, 0x03},

        {0x060A, 0x00},

        {0x060B, 0xE8},

        {0x060C, 0x03},

        {0x060D, 0x00},

        {0x060E, 0x88},

        {0x060F, 0x13},

        {0x0610, 0x88},

        {0x0611, 0x13},

        {0x0612, 0x8A},//{0x0612, 0x0E},//ALPHA0

        {0x0613, 0xE3},//{0x0613, 0xB2},

        {0x0614, 0x09},//{0x0614, 0x08},//ALHPA2/ALPHA1

        {0x0615, 0x82},//{0x0615, 0x82},//BETHA0//ALPHA2

        {0x0616, 0x62},//{0x0616, 0x62},//BETHA0

        {0x0617, 0x42},//{0x0617, 0x42},//BETHA1//BETHA0

        {0x0618, 0xD8},//{0x0618, 0xD8},//GAMMA0

        {0x0619, 0x47},//{0x0619, 0x47},

        {0x061A, 0x21},//{0x061A, 0x21},//GAMMA1/GAMMA0

        {0x061B, 0xCB},//{0x061B, 0xCB},//DELTA0

        {0x061C, 0xC4},//{0x061C, 0xC4},//DELTA1//DELTA0

        {0x061D, 0x05},//{0x061D, 0x05},//ALPHA3//DELTA1

        {0x061E, 0x7D},//{0x061E, 0x7F},  R

        {0x061F, 0x00},

        {0x0620, 0x00},

        {0x0621, 0x00},

        {0x0622, 0x4F},//{0x0622, 0x0B},  S(7:0)

        {0x0623, 0x01},//{0x0623, 0x02},  S(15:7)

        {0x0624, 0x00},//  S(23:16)

        {0x0625, 0x00},

        {0x0626, 0x01},//{0x0626, 0x26},

        {0x0627, 0x00},//{0x0627, 0xB0},

        {0x0628, 0x00},

        {0x0629, 0x10},

        {0x062A, 0x27},// Phase Threshold

        {0x062B, 0x20},

        {0x062C, 0x44},

        {0x062D, 0xF4},

        {0x062E, 0x01},

        {0x062F, 0x00},

        {0x0630, 0x20},

        {0x0631, 0x44},

 

The first problem is that I do not understand why the calculated DDS frequency is 80.400MHz which should be 80MHz regarding to DDS frequency formula on page 33 of AD9548 datasheet... Using the extracted parameters and changing FTW to 0x1AAAAAAAAAAB (FTW= 2^48 *80/768) where 768MHz is the system clock, I have an OK 20MHz... I am not sure if the phase if it is good too.

 

About AD9523-1 I changed as below (reference config file no-OS/AD9523_cfg.h at master · analogdevicesinc/no-OS · GitHub):

 

80000000, //vcxo_freq
/* Single-Ended Input Configuration */
0,  //refa_diff_rcv_en
1,  //refb_diff_rcv_en
1,  //zd_in_diff_en
0,  //osc_in_diff_en
1,  //refa_cmos_neg_inp_en
0,  //refb_cmos_neg_inp_en
0,  //zd_in_cmos_neg_inp_en
1,  //osc_in_cmos_neg_inp_en
0,  //refa_r_div
0,  //refb_r_div
4,  //pll1_feedback_div
2000,   //pll1_charge_pump_current_nA
1,  //zero_delay_mode_internal_en
0,  //osc_in_feedback_en
3,  //pll1_loop_filter_rzero
420000, //pll2_charge_pump_current_nA
2,  //pll2_ndiv_a_cnt
9,  //pll2_ndiv_b_cnt
0,  //pll2_freq_doubler_en
1,  //pll2_r2_div
4,  //pll2_vco_diff_m1
4,  //pll2_vco_diff_m2
0,  //rpole2
2,  //rzero
2,  //cpole1
0,  //rzero_bypass_en

 

It causes the VCO in the second PLL turn to 3040MHz. Measuring the frequencies by oscilloscope, It generate the clocks as expected but the first PLL is not lock when AD9523_READBACK_0 is read.

 

-Ehsan

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