i am not able to understand how Blackfin CPU BF524 and FPGA is helpful in EVAL-ADV8005-SMZ. can we do OSD and quad picture in one picture using ADV-8005 only without the help of Blackfin processor and FPGA?
please kindly extend your help. Thanks
The Blackfin 524 is the Host CPU in the system. It has nothing to do with the video outside of controlling the part.
The FPGA is just for configuring how the TTL bus is routed between ADV8005, ADV7842, and a header. It also does no processing of video of any kind.
You can't do 4 pictures into 1 in a single ADV8005 at all-- it doesn't have 4 inputs. You would need to use 3 of them in sequence to do it.
thanks DaveD for response.
i need another help. is there any chip which can do quad picture in one picture alone without using it in sequence or some better chip for picture in picture ?
When you speak of quad picture, I assume you are mostly likely speaking of Video Surveillance Controllers where you can have 4 images displaying at the same time. These controller generally work work with CVBS. Some do have OSD over lay functions. ADI does not have a single chip solution for quad video like a surveillance controller.
i would like to use the 3 sequence chips design, but now i have four 4k2k inputs, do the OSD's scaler support to downscale the 4k2k signal to 1/4 size 1080p signal? you mean the first chip blend 2 input signals,and the second chip capture the first output merge the third input signal,and so on. then, we must use the OSD's blend block, and my 4 inputs must input from the OSD TTL PINS, and do the parallel TTL pins support 4k2k signals?
how can i link these 3 chips? could you provide the block diagram to me? thanks!
It's not something we have a reference design for. For 4 4k inputs it's a lot more complicated since ADV8005 can only downscale 1 input from 4k. I think you'd need 5 in that case. Something like this:
Chip 1) Takes Input #1 and puts out 1080p #1 to Chip 3
Chip 2) Takes Input #2 and puts out 1080p #2 to Chip 4
Chip 3) Takes Input #3 and scales down to 1080p #3 and does a top/bottom 960 x 1080 #1 with 1080p #1 & #3
Chip 4) Takes Input #4 and scales down to 1080p #4 and does a top/bottom 960 x 1080 #2 with 1080p #2 & #4
Chip 5) Takes top/bottom #1 and top/bottom #2 and merged them to make a 1920 x 1080 with all 4 inputs
The parallel pins support 4k/2k but at 2 pixels per clock which is the output of ADV7619.
This would be a very complicated way to solve the problem though.
thanks for your reply,now i clearly understood your solution,but such as you said,it is too complicated,so now i adjuest the maximam input's resolution to 1920x1080_60P.
i think i can still use 3 chips to merge 4 under or equal 1080P inputs to one 4K2K output, how do you think?
if my inputs include the interlace format such as 1920x1080_50I, does the OSD's scaler support de-interlaced? i see the SVSP does not support the interlace input.
Yes, for 1080p and below you could do:
Chip 1) Takes input #1 on TMDS and input #2 on TTL pins and outputs a top/bottom #1 of 960x1080
Chip 2) Takes input #2 on TMDS and input #3 on TTL pins and outputs a top/bottom #2 of 960x1080
Chip 3) Takes merges top/bottom #1 and top/bottom #2 into a full 1920x1080 image
You would need transceivers (for TMDS) / receivers (for TTL) on the inputs assuming they are all HDMI.
You have the same problem converting 1080i to 1080p as you would with 4k-- only 1 input can do that.
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