I do not know which is more problem, SSB Noise Floor or CP Noise.

Which is affect to total phase noise, SSB Noise Floor or CP Noise?

How I can calculate total phase noise?

BR, Tomo

I do not know which is more problem, SSB Noise Floor or CP Noise.

Which is affect to total phase noise, SSB Noise Floor or CP Noise?

How I can calculate total phase noise?

BR, Tomo

The charge pump is just one of many sources of noise that contribute to the "total" phase noise in a modern PLL synthesizer. All sources of noise need to be minimized as much as possible to achieve the lowest phase noise performance. Generally speaking, the noise floor itself won't significantly impact the total noise until it is within 10dB. Typically this occurs at offsets between 1MHz and 10MHz from the carrier, this is evident by the change in the phase noise slope. The HMC783LP6GE incorporates a PLL that is very similar to the HMC703LP4. Please refer to pages 6-15 through 6-17 of the attached HMC703 datasheet for a good primer on noise contributors and total phase noise. These pages also include VCO and PLL Figure of Merit (FOM) equations to estimate the noise floor of the PLL and VCO under specific operating conditions and at a specific frequency. The noise from the charge pump is dependent not only on the current setting but also on where it's operating. Pages 6-4 to 6-5 of this same datasheet present plots of the PLL FOM floor vs. CP current, mode of operation, temperature, reference waveform and input power. Notice Figure 8 at the top of page 6-5; as the CP current decreases from 2.5mA to 0.5mA the PLL FOM floor increases 10dB. Now notice Figure 10 that uses the optimal CP current setting of 2.5mA and illustrates the effect on the PLL FOM as the CP voltage is varied. Maintaining CP operation between 0.8 and 4.2Vdc is important to not only for optimum phase noise but also to minimize spurs.

The charge pump is just one of many sources of noise that contribute to the "total" phase noise in a modern PLL synthesizer. All sources of noise need to be minimized as much as possible to achieve the lowest phase noise performance. Generally speaking, the noise floor itself won't significantly impact the total noise until it is within 10dB. Typically this occurs at offsets between 1MHz and 10MHz from the carrier, this is evident by the change in the phase noise slope. The HMC783LP6GE incorporates a PLL that is very similar to the HMC703LP4. Please refer to pages 6-15 through 6-17 of the attached HMC703 datasheet for a good primer on noise contributors and total phase noise. These pages also include VCO and PLL Figure of Merit (FOM) equations to estimate the noise floor of the PLL and VCO under specific operating conditions and at a specific frequency. The noise from the charge pump is dependent not only on the current setting but also on where it's operating. Pages 6-4 to 6-5 of this same datasheet present plots of the PLL FOM floor vs. CP current, mode of operation, temperature, reference waveform and input power. Notice Figure 8 at the top of page 6-5; as the CP current decreases from 2.5mA to 0.5mA the PLL FOM floor increases 10dB. Now notice Figure 10 that uses the optimal CP current setting of 2.5mA and illustrates the effect on the PLL FOM as the CP voltage is varied. Maintaining CP operation between 0.8 and 4.2Vdc is important to not only for optimum phase noise but also to minimize spurs.