I am trying to build the HDL reference design for the FMCOMMS2 board on a ZedBoard platform.
I have successfully followed the instructions in ADI Reference Designs HDL User Guide [Analog Devices Wiki] to download the master branch and build all the libraries using Vivado 2013.4. However when I run the system project, the tool exits with a timing constraint failure. This prevents me from exporting the design to the SDK.
I have attached the timing log file. I'm new to FPGA design, so can anyone tell me if there's something obvious I've missed or if there's an issue with the latest master version?