Follow snapshot is the pll lock status from AD9540, is it an analog pll lock signal. I am wondering if the PLL is in normal locked status.
When CFR2<24> is set to 0 (default) and PLL_LOCK is a status indicator the response is as follows.
A constant high level (3.3V) on this output indicates that the loop is unlocked.
There will be no pulses when the loop is significantly out of lock. "Significantly out of lock" means that the input edges to the PFD are on a cycle by cycle basis always greater than approximately 0.5ns apart.
A constant low level (0v) indicates that the edges are aligned closer than approximately 0.5ns and remain so on a cycle by cycle basis. This is a locked state.
Some pulsing may be observed during the locking process whenever on a cycle by cycle basis the separation toggles between being within ~0.5ns to being outside of ~0.5ns. The loop is not locked at this point. There are just samples during the phase slipping process where the edges are aligned for that cycle.
Also, we must state that there is a bug with this function. If there is no Reference input signal at all. The locking circuitry may not reset and will give a false lock indication.
That's very interesting theory. But my observation is on the other side, when the PLL output frequency matched my settings, I catch the PLL_LOCK status waveform in my first post, when the PLL output went sideways, the PLL_LOCK status is complete low level. There is always reference input signal and the CFR2<24> in default value.
Retrieving data ...