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AD5161 Digi-Pot I2C Bus timing

Question asked by ricky on Oct 15, 2014
Latest reply on Oct 23, 2014 by ricky

Hi All,

 

My customer is considering to use AD5161 Digi-Pot for his new design.

Prior to the design work, he sent me a confirmation of I2C bus timing specification of AD5161 in its Data Sheet.

Page 5 of the Data Sheet says the Data Hold Time (t6) is 0.9us max.

Does this means that data(SDA) should be stable for 0.9usec after falling edge of clock(SCL)?

What is the minimum value of t6?

This customer has failed experience with other device which has I2C bus.

He sent SCL and SDA to the I2C device from MCU with a timing between falling edge of SCL and beginning of SDA change is zero,

(This is equivalent to t6=0 in AD5161 case)

In his previous design, the I2C device was not operate correctly.

Because of this experience, we would like to ask your confirmation.

If AD5161 requires that data(SDA) should be stable for 0.9usec after falling edge of clock(SCL), AD5161 I2C bus doesn't comply with Philips I2C bus specification, he said. The I2C device should be work correctly with 0usec, he said.

 

Thank you for your help.

Best Regards,

Ricky

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