my questions are mostly for guys from ADI.
Question 1: What about cycle timing on new Blackfin+ architecture? Did you change execution time in CPU cycles for Jump/Call instruction?
In BF5xx and BF60x are using memory layouts totally different from BF70x.
Internal memory (L1, L2, MMRs and more) -0xC000 0000 … 0xFFFF FFFF
External SDRAM/DDR/DDR2/Async – 0x0000 0000 … 0x4000 0000
Internal memory (L1, L2, MMRs and more) -0x0000 0000 … 0x3FFF FFFF
External SDRAM/DDR/DDR2/Async – 0x4000 0000 … 0x9000 0000
In uClinux relative jump was used (except - execution from external Flash/SRAM). On new Blackfin+ architecture relative jump between L1/L2 and DDR2 memory is not possible because of big memory hole (> 24bit address). Did you plan new method of branch operations for OS interaction (when L1&L3 code execution take place)?
Question 2: What is the difference in CPU cycles between Jump.s and Jump.a?