A bit of background...
I previously modified the AD9279 reference design to become a 4 channel ADC interface and verified it was working with the AD9633 eval board connected to an ML605 across the FMC interposer. A small modification to the interposer had to be made so two clocks (DCO and FCO) can be supplied to the FPGA. I was able to read data correctly in chipscope and through the Microblaze UART interface.
I am now porting this design to the ZedBoard (ZC702). I built a system from the base up, with only a minor modification: ISERDESE1 became ISERDESE2. I understand the IO primitives in the design are different for the ZC702 architecture, but the SERDES is the only one I found to be different. I did not make any other changes, as I do not know what other changes need to be done.
I am trying to first verify that the ADC capture is working, but all four channels read nothing in ChipScope. It seems the adc_clk signal is working, however, since the ChipScope core runs, and halts when the clock is turned off. It also seems like the trigger signal mon_valid based on data_select is working too, since the core triggers.
I double checked the pinouts in the UCF file, and I know the ADC is configured to output data across the 4 P/N lanes (DDR, 1 lane interface) as I have it programmed through SPI and can probe the right pins on the eval board or the interposer.
I also know the ChipScope cores are connected correctly as assigning known data to the mon_data signals (bypassing the output of the SERDES) are read in the analyzer.
To those who have experience with this design and with the Zync architecture, what do you think is the problem here? What needs to be changed in the input buffering and deserializing components to port this design to the ZedBoard/ZC702?