I am trying to write my own low level driver for this device and need to know how to set/determine the output frequency of the data_clk. Where is this located in the documentation?
Please use the ADI provided Linux or No-OS drivers.
Digital sample clock - aka symbol rate or BB rate is reported.
In LVDS mode:
DATA_CLK is two times symbol rate in 1RX1TX mode
DATA_CLK is four times symbol rate in 2RX2TX mode
so in LVDS 2RX2TX mode at 61.44 MSPS the maxiumum DATA_CLK of 245,76 MHz achieved.
The DATA_CLK frequency generated depends on the system architecture (such as, number of RF channels, degree of over-sampling, and bandwidth mode).
You should use ADI provided API drivers to configure the part.
so you are saying that there is no way for me determine what data_clk will be based on other system parameters?
ADI provided drivers configure the part for a desired configuration. DATA_CLK frequency is configuration dependent. The only constraint on DATA_CLK is not to exceed the maximum specified frequency.
Moved to Linux Drivers for additional information on where DATA_CLK frequency is reported in software.
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