We have a system where we need to output standard-def NTSC (interlaced) but the video data we have is in a progressive format.
The video input to our system is 30 bit RGB. The S_HSYNC and S_VSYNC pulses that are being presented are correct in frequency (S_VSYNC is just a bit under 60 Hz) and in polarity (active low); all as expected.
In our specific system, we are configuring for NTSC input, per table 72 on page 97.
In the Rev A data sheet, page 56, in the section entitled "SD NONINTERLACED MODE" it indicates that register 0x88, bit 1 be set to 1. Either setting register 0x88, bit 1 or clearing this same bit seems to have no effect.