hello I want to put my on data on TX channel of AD-9364 in LVDS mode. I want to send them from FPGA to Board. The problem is that in this mode I have only 6 bits of data available to transmit 12 bits of data. i.e. on one rising-edge of dac-clock I put MSB of that 12 bits and in the second rising-edge of the clock I put LSB bits. but I lost half of my data. I tried to understand that how it is managed by the HDL reference design code presented in wiki analog, but it looked complicated. your help is really appreciated.
with best regards