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AD9361 PLL regs settings

Question asked by FreddyS on Oct 7, 2014
Latest reply on Oct 7, 2014 by tlili

Dear Supporter

I am using the AD9361 in my own board. I can read and write registers correctly.

I cannot get a working PLL.

The clock input is 30.72Mhz

I would like to get at the LO output 902.2Mhz.

I am setting the registers according the example provided in the design package files.

It seems I am missing something...

Do you have a set of commands setting the relevant registers?

Thanks for your support.

F.

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