We are using a AD9915/PCBZ in combination with a Xilinx ZC702 eval board. We are using a Xilinx FMC XM105 debug board to access the clock and I/O pins on the FPGA. The sync clock output on J100 of the DDS board is connected to J9 on the Xilinx debug board. This input connects to a multi-region clock capable pin on the FPGA that is setup for LVCMOS33 operation. When measuring the J100 output on the scope, the 3.4V, 125 MHz sine wave shown in dds_clock_output.png is obtained. When J100 is connected to J9, the sync clock signal is attenuated as shown in dds_125mhz_sync_clk_at_j9.png. An MMCM in the FPGA does not lock to the clock, and the IBUFG used with the J9 input pin shows active high constantly. Do you know if a clock distribution board is needed when using the AD9915/PCBZ board with a FPGA?