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External memory read timing about ADuC7019_20_21_22_24_25_26_27_28_29

Question asked by sofy Employee on Oct 7, 2014
Latest reply on Oct 22, 2014 by sofy

Hello,

I'd like to ask about external memory read timing of ADuC7026.

According to datasheet page 14, Table 3. External Memory Read Cycle,

tDATA_BEFORE_RD_H is specified min 16ns.

tDATA_AFTER_RD_H is specified min 8ns, typ "+ (! XMxPAR[9]) × CLK"

 

Is that mean memory read "setup time" is min 16ns after RS rising?

Also can I think that "hold time" is same as tDATA_AFTER_RD_H ?

 

About "+ (! XMxPAR[9]) × CLK"

Is it mean if MxPAR[9] == 0, then tDATA_AFTER_RD_H become 8ns + 1 clk ?

(I'd like to confirm about "!" usage in the datasheet.

 

Thank you for your help in advance.

Best regards,

Sofy



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