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21369 SPI receive DMA FIFO problem

Question asked by Tyrone on Oct 4, 2010
Latest reply on Oct 6, 2010 by DivyaS

Hi All,

 

I am trying to setup a communication protocol between SHARC 21369 and FPGA of my design.

 

Both are communicating via SPI and FPGA as master where 21369 as slave.

 

The problem that i have encounter is by setting up the SPI receiver in 21369 as core driven is too slow to handle the data from FPGA(50Mbps). So I changed the receiver as DMA driven.

 

Here is the big question. After setting up the receive DMA at the 21369, I notice the DMA 4-deep FIFO will not be writing into the internal memory if the protocol transfer size is smaller than 4 words. Unfortunately my packet size coming from FPGA can range from 2 words to 256 words, I have no way to predetermine the size of the DMA count.

 

Looking for idea to solve this.

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