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AD9361 Data Interface Question

Question asked by labianco on Oct 6, 2014
Latest reply on Oct 6, 2014 by rbrennan

Guys,


I am trying to understand the data interface to this chip.  When in CMOS, dual port, half duplex mode; the BBP drives the ENABLE and the TXNRX lines.  My understanding is that it asserts the enable high with TXNRX low to request any received data.  The AD9361 responds by pulsing/asserting the RX_FRAME signal to indicate RX_DATA is present. 


If the second ENABLE pulse is never sent, the AD9361 will just keep sending data to the BBP? 

On pg. 92 of UG-570: for a Dual port half duplex SDR application the data rate achievable is 61.44 Mbps.  Is this also the ADC sample rate or just the rate at which data is read from the AD9361?


I would like to use this device in dual port half duplex SDR, TDD mode.  The UG-570 doesn't have a timing diagram of this mode; is this mode valid?


Thanks,

Nick

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