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Generate multiple clocks from rx_clk_in_#

Question asked by nikbartz on Oct 3, 2014
Latest reply on Oct 3, 2014 by larsc



I am using the FPGA reference for the FMCOMMS3 board plugged to a Xilinx ZC706 board.

I am implementing my own Transmitter at the programmable logic area of the XC7Z045 device using custom VHDL coding and I am interfacing it with the remaining of the reference design without affecting the rest of its functionality (e.g., generating tones and playbacking waveforms from files). I didn't face any implementation problems until now (ISE 14.4), working with 20 MHz signals. I am also using the precompiled coefficients for the FIR filter for an LTE signal of 20 MHz (30.72MHz sampling rate)

However, while doing on-board testing some doubts were raised regarding the rx_clk_in_ clock:

  1. The rx_clk_in_p and rx_clk_in_n are constrained at 250 MHz. If I set the sampling frequency of the Tx using the ADI IIO Oscilloscope GUI (FMCOMMS tab) at 1.92 MHz for a RF bandwidth of 1.4 MHz, will then the rx_clk_in_# (shared among the receive and transmit baseband paths) be also 1.92 MHz?
  2. Do I still need to constraint the design at 250 MHz? Is it possible to relax this constraint?
  3. If the configuration of the rx_clk_in_# described before is indeed giving me a 1.92 MHz clock for the FPGA design, is there an easy out-of-the-box way to synthesize a higher clock from this one (3.84 MHz and 7.68 MHz respectively, necessary for internal operations of the custom VHDL-based Tx), considering that both the MMCME2_ADV and PLLE2_ADV of Xilinx do not accept an input clock of 1.92 MHz? Any other suggestion will be welcome.


Thank you very much in advance.