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FMCOMMS1: Clock Genarator adjustments...

Question asked by ehsantelecom on Oct 2, 2014
Latest reply on Nov 2, 2017 by timmy

Hello everybody...

I am using FMCOMMS1 and ZC706 for a project. I need to have 40MHz (and the factors) with maximum precision on the board to sample accurately. I decided to change the crystal oscillator (Y1) from 122.88MHz to 80MHz physically. Now, I have some problems with AD9548 initialization. There are lots of information in the datasheet!

Having minimum amount of changes in the driver, do you have any suggestion? My efforts so far:

I kept 30MHz coming from FPGA to the component and I changed "Free running frequency tuning word" from 0x28f5c28f5c29 to 0x1AAAAAAAAAAB which is not very effective because the output signal is drifting to higher frequencies very rapidly. What other registers should I manipulate?


For the people have not access to the driver's files:


/* System clock settings */

    0,          //sys_clk_ext_loop_filter_en

    0,          //sys_clk_charge_pump_manual_mode_en

    0,          //sys_clk_pll_lock_detect_timer_dis

    0x03,      //sys_clk_charge_pump_current

    0x00,      //sys_clk_pll_lock_detect_timer

    0x28,      //sys_clk_fedback_div

    0,          //sys_clk_m_div

    0,          //sys_clk_2x_mul_en

    1,          //sys_clk_pll_en

    1,          //sys_clk_source

    0x13de43,  //sys_clk_period

    0x000001,  //sys_clk_stability


    /* DPLL Setting */

    0xAA,      //dpll_tunning_word0

    0xAA,      //dpll_tunning_word1

    0xAA,      //dpll_tunning_word2

    0xAA,      //dpll_tunning_word3

    0xAA,      //dpll_tunning_word4

  0x1A,      //dpll_tunning_word5

    0x000000,  //dpll_pull_in_range_limit_low

    0xffffff,  //dpll_pull_in_range_limit_high

    0x00,      //dpll_dds_phase_offset

    0x0000,    //dpll_closed_loop_phase_lock_offset_low

  0x0000,    //dpll_closed_loop_phase_lock_offset_high

    0x03e8,    //dpll_incremental_phase_lock_offset

    0x0000,    //dpll_phase_slew_limit

    0x7530,    //dpll_history_acc_timer

    0x00,      //dpll_history_mode

    30000000,  //dpll_out_freq


    /* Clock distribution synchronization */

    0,          //clock_distr_ext_resistor

    0,          //clock_distr_high_freq_mode

    0x00,      //clock_distr_sync_source

    0x02,      //clock_distr_automatic_sync_mode


    /* General settings */  

    0x00,      //watchdog_timer

    0x1ff,      //aux_dac_full_scale_current

    0,          //aux_dac_shutdown

    0x01,      //ref_profile_sel_ssm_startup


    /* Reference profiles */

    0,          //num_ref_profiles

    0,          //ref_profiles