In the past month, I've modified the reference design for the AD9279 to capture data from a 4 channel ADC card. I am evaluating two ADCs, a TI product, and the AD9633. The interface with the TI product functions well, which means my modifications are not a problem. However, when interfacing the same design with the AD9633 evaluation board, I am running into a problem.
When implementing the FPGA design with the UCF file edits for this board, I am getting place and routing failures due to the location of the input buffers for the clock. The problem seems to occur when using the pins H4 and H5 (LOCA10 and B10) which are the FMC_LPC_CLK0_M2C N&P pins. Any other pins allow the design to be built without errors.
I do have doubts about the schematic and how I read the pinout, however, and I'd like a second and third opinion. From what I found for the evaluation board, and the FMC interposer schematics, bit clock is on H4/H5, frame clock is on G6/G7, and the channels are on G18/G19, G15/G16, G12/G13 and H10/H11. Can anyone confirm or deny these conclusions? The schematics are cryptic with inconsistent naming signals over multiple documents.
I'd appreciate some input to help me get the AD9633 eval board working as I have the TI one, because I need to make a decision on which to use moving forward, and would go with the AD9633 if I can get past this issue.