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How to verify digital loopback in AD9364?

Question asked by jinojs on Oct 1, 2014
Latest reply on Nov 22, 2014 by jinojs



We are using AD9364 with Xilinx KC705.

Before start using our application (algorithm), I'm trying to verify the digital loopback using the reference design of AD9361. I believe it is implemented in the function: ad9361_dig_tune in ad9361.c

I need to use the PRBS sequence. Also I'm using the reference design by using DDS (DAC_DMA is not enabled).


Currently I'm able to see the waveform for ADC channel I and Q on the ILA (Integrated Logic Analyzer) in Vivado. But I cannot see any data on DAC data I and Q.


How exactly can I visibly conclude that the digital loopback is working fine? I want to send some data (PRBS) from FPGA to AD9364 and get it back in FPGA.

I have enabled XILINX_PLATFORM in main.c


In the code (function ad9361_dig_tune), I see 'ad9361_bist_prbs(phy, BIST_INJ_RX);'. Does this mean that the data is only injected at the RX level? Is that the reason I don't see anything on DAC? I don't see BIST_INJ_TX getting used anywhere in the code.

In function ad9361_dig_tune, I also see the below function calls.


  ad9361_bist_prbs(phy, BIST_DISABLE);

  ad9361_bist_loopback(phy, 1);

Is this 'ad9361_bist_loopback' responsible for the digital loopback?


I have followed the wiki ( and and created the reference design project and performed the initialization of AD9364 successfully.


Please guide me in performing the digital loopback on this setup at the earliest. After that I need to verify the RF performance and start adding our algorithm.


Thank you very much for your support,