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ADV7619 timing question - t11, t12 maximum allowed values?

Question asked by Lionelwallace Employee on Sep 30, 2014
Latest reply on Oct 2, 2014 by GuenterL

Customer Question:

I’ve been doing timing analysis for the FPGA interface to the ADV7619. The ADV7619 data sheet seems to leave out the maximum numbers for the t11 (End of valid data to negative LLC edge) and t12 (Negative SCLK edge to start of valid data). The maximum numbers are fairly important to being able to properly constrain that interface.


Please provide max values for t11 and t12