AnsweredAssumed Answered

ADN4665 behavior

Question asked by eltury on Sep 29, 2014
Latest reply on Oct 1, 2014 by ConalW

Greetings,

I am using this device to drive a "long" distance SPI bus wherein the clock, and data to read back, travel the same distance on the cable.

The delays I measure for the signals match the expected delays per the cable mfr. spec. The clock signal has equal rising and falling edge delays but the data experiences a longer delay for the rising edge as the falling edge essentially shortening a bit.

 

Now I know this is weird so I'm thinking a bad chip? I only have one board to measure this on. The system is working fine for shorter cable lengths but for a 100' cable I see the phenomenon cause the clock edge to not line up with the center of a bit.

 

Has anyone ever seen this? Any thoughts on what else could be happening?

 

Thank you.

 

Edd

Outcomes