I am trying to build the FMCOMMS5 reference design but I'm encountering a few errors. The most prominent errors are related to the set_clock_groups commands in the constraints file. I'd like to know if there's a working version of this. Secondly, there is an error about port width mismatch that seems rather important: I've attached my synthesis log.
CRITICAL WARNING: [BD 41-1228] Width mismatch when connecting input pin '/util_dac_unpack_0/dma_data'(1) to net 'axi_ad9361_dac_ddata'(128) - Only lower order bits will be connected, and other input bits of this pin will be left unconnected.
Thank you for the help.