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AD9361 ssues with q0/i1/q1 on latest kernel and Vivado HDL

Question asked by njp on Sep 24, 2014
Latest reply on Sep 27, 2014 by njp



I have my own board with a Zynq (xc7z020clg400-2) and AD9361. I've been working on a project where I modified older (back from around May before the adc_pack and dac_unpack?) source code on the "hdl" repo to make a bitstream with Vivado as well as your kernel from around that time (3.13.0-g5aa6400). I'm now trying to update to the latest kernel and HDL and having issues.


A couple things about my design:

  • different FPGA package... though I'm quite confident I modified the and TCL scripts appropriately, and my top-level I/O constraints are proven
  • TX is not used and not wired to the FPGA and I have tied pins on the 9361 appropriately per the datasheet
  • the Sync pin on the 9361 is grounded
  • Use external reference clock (I've set this in the devicetree)
  • 1GB DDR


I have verified the latest HDL and latest kernel do work on the ZC702.  The system_bd.tcl and your TCL scripts for the ZC702 were just modified for my FPGA/memory config, and then I modified system_top.v and changed the top-level I/O that I don't have to be Verilog wires instead of inputs/outputs.


I made the following modifications to ad9361.c:

  • on boot, the message "Tuning TX FAILED!" appears. I did the following to remove the change to clock delay:

    if (err == -EIO) {


      ad9361_spi_write(phy->spi, REG_RX_CLOCK_DATA_DELAY,


      ad9361_spi_write(phy->spi, REG_TX_CLOCK_DATA_DELAY,



      err = 0;

    } //else {

      phy->pdata->port_ctrl.rx_clk_data_delay =

        ad9361_spi_read(phy->spi, REG_RX_CLOCK_DATA_DELAY);

      phy->pdata->port_ctrl.tx_clk_data_delay =

      ad9361_spi_read(phy->spi, REG_TX_CLOCK_DATA_DELAY);



When I look at the Vivado Chipscope, the i0 stream looks good with valids and data spaced as expected, but q0/i1/q1 never have valids (and they never trigger) and the data values stay constant.


I'm thinking this is something related to the kernel and not the HDL, because the HDL changes were pretty straightforward and I had similar success before (and I had to muck with the dig_tune as well then).  Also, before I made the dig_tune change in the kernel, the i0 valids seemed random.


Any help/guesses at what the problem might be is appreciated. Thanks!