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ADV7181D 12bit RGB DDR mode

Question asked by daisu on Sep 23, 2014
Latest reply on Oct 8, 2014 by daisu

Hello all,

I have one questions about ADV7181D.


When we use ADV7181D at 12bit RGB DDR mode,

order of output data at rising edge and falling edge of LLC is opposite to order described in manual_table.53.

(first half of B and G at falling edge of LLC, second half of G and R at rising edge of LLC)



WE think that setting of Reg 0x37 =0  is not invert.

Is it correct ?


If there is any other mistake of setting, coudl you give me your advice ?


CUstomer's registe rsettings are below

  Reg 0x37=0x01

  Reg 0x89=0x08

  Reg 0xc9=0x08