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AD9361 clock BBPLL frequencies for digital TV

Question asked by CannaGiu on Sep 24, 2014
Latest reply on Sep 26, 2014 by tlili

Using the AD9361 BBPLL I've some difficulty to generate the exact DAC sampling frequency for all required digital TV broadcasting signal bandwidths using the internal BBPLL using a single Refclock frequency. The FRAC modulus is fixed to 2088960 and isn't programmable like ADF435x PLL+VCO series.

For my application the reference clock is 10MHz (that cannot feed directly the AD9361), but I can use a clock generator like AD9524 to lock a an internal 10MHz reference (using a 1st PLL to clean the external 10MHz) and use the AD9524 second PLL to generate the clock that feeds AD9361.

The required frequencies at BBPLL output are:

640/7  MHz
512/7  MHz
448/7  MHz
384/7  MHz
320/7  MHz
1048/71 MHz

16384/189 MHz
14336/189 MHz
12288/189 MHz
10240/189 MHz


Can anyone help on how to generate these frequencies at BBPLL?

It's suitable to generate the Refclock using a clock generator like AD9534? The AD9534 VCO+PLL phase noise performances are acceptable for clocking the AD9361?

I want to obtain same performances result like the AD-FSCOMMS3-EBZ (that uses a fixed 40MHz quartz as reference clock) but using the external reference input.