I was trying to bring up the new Vivado version github HDL for the FMCOMMS1 design for ZC702 board to see if I could get it running. When I looked at the built block diagram that is generated I noticed that there appears to be no connection from the AD9643 block into the Xilinx write FIFO that is used to input to the DMAC block.
The updated Verilog for AD9643 now brings out the raw adc_data_0 and adc_data_1 with adc_valid_0 and adc_valid_1 where there is no longer connection coming from it, axi_ad9643.v, for adc_dma_wdata or adc_dma_wr which is what use to be connected to the DMA engine data input. In the fmcomms1_bd.tcl it appears the axi_ad9643.v still needs to support these DMA signals which have been removed from it for some reason.
Perhaps there is a new code block that is missing between the ADC and DMA sections.
or I am missing something..
I know that there is a lot of updating going on with the new ADI Vivado HDL githib site. Has the fmcomms1 design HDL for Vivado been checked out to see if still works with all the changes in the HDL code?
From what I see it looks to be broken for the ADC side per above, that there is on longer any data connections from the ADC into DMA.