I'm attempting to build the FMCOMMS5/ZC706 reference design. I am at Vivado version 2014.2. I have downloaded the latest hdl from https://github.com/analogdevicesinc/hdl. I have run system_project.tcl in directory hdl/projects/fmcomms5/zc706.
I originally got the same error as described in https://ez.analog.com/thread/42721 and implemented the solution. But now I am getting additional errors. Specifically, there are 4 AXI interconnect IPs which are at the same version but different revision. I cannot generate files from these since they are locked so its preventing me from simulating. But I am also prevented from updating them apparently because the revision isn’t critical enough. The attached JPG shows the IP status window and simulation error. The simulator_language property is already set to "mixed" as suggested by the error message.
Any idea how I can generate the simulation files for the AXI interconnect?