I have a system consisting of a motherboard with up to 8 daughterboards, each with an ADE7878. One TCXO 16.384Mhz crystal drives all 8 chips. Initially, with the TCXO output directly linked to all 8 CLKIN pins, the integral LDO regulators won't fire up (no DVDD or AVDD). With the TCXO coupled to all CLKIN's with a 10nF cap, it starts to work. The signal is very small and I assume that capacitive coupling allows it to find the right level for the CLKIN to work. I can see a 16.384MHz oscillation no problem but I want to be sure that the ADE7878 is working at the right frequency to confirm that adding a single cap is sufficient (and doesn't need any extra buffering).
A steady output in period register should confirm this. The datasheet 'Period Measurement' says 50Hz should give a reading of around 5120 - but readings give a fairly random between 2300 and 1200 (with mains voltage on phase A). This problem could be solved by connecting the neutral input of each ADE7878 to DGND rather than real mains neutral. It now gives a steady 5122 +/- 2 which equates to 50Hz +/- 0.04%. Why should this be and is it OK? There are no recommendations in this area from AD. Additionally, the AD reference design shows a balanced 2R2 load on each current input. It appears that these resistors shouldn't be fitted and testing with them omitted gives a correct and predictable voltage (eg 100A CT gives 0.33Vac at 100A). I am assuming it is OK to do this.