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TS201 refresh cycles

Question asked by twilkers Employee on Sep 28, 2010
Latest reply on Oct 12, 2010 by jeyanthi.jegadeesan

Hi,

 

Customer is having trouble getting SDRAM working on new TS201 boards.

 

System uses PC133S SODIMM modules which are connected one apiece to multiple TS-201s. There are no Host or Multiprocessor busses in use. The bus has just SDRAM and a slow NVRAM. ACK for the NVRAM is generated by the FPGA.

The trouble is:

  • SDRAM      works for read and write, but is not persistent. The first bit errors      start to appear in the time it takes to write 16M locations.
  • No      self-refresh or auto-refresh is generated from the TS-201.
  • During      memory tests the SYSTAT register reads 0x00003200 meaning that no SDRAM      command error was detected, that the processor is not the host master, and      that bus lock is not asserted.

 

Overall, the external SDRAM observation is,

1. Pre-charge
2. Several auto-refresh cycles.
3. Write to the Mode Register
4. No refresh cycles after that.

We can read and write the memory. However there are no refresh cycles.

 

So the question is what will prevent the external DRAM controller from issuing refresh cycles?
It did not put the SDRAM in self refresh mode.

 

Customer has tried the following setup sequences.

 

    xr0 = SYSCON_MEM_WID64;;
     SYSCON = xr0;;
     xr0 = SDRCON_INIT    | SDRCON_RAS2PC5 | SDRCON_PC2RAS3 |
           SDRCON_REF2200 | SDRCON_PG512   | SDRCON_CLAT2   |
           SDRCON_ENBL ;;
     SDRCON = xr0 ;;

 

However we have tried others, like,

 

        xr0 = SYSCON_MS0_IDLE | SYSCON_MS0_WT3 | SYSCON_MS0_PIPE4 |
             SYSCON_MS0_SLOW | SYSCON_HOST_WID64 | SYSCON_MP_WID64 |
             SYSCON_MEM_WID64 ;;
         SYSCON = xr0;;
         xr0 = SDRCON_INIT    | SDRCON_RAS2PC5 | SDRCON_PC2RAS3 |
               SDRCON_REF1100 | SDRCON_PG512   | SDRCON_CLAT2   |
               SDRCON_ENBL | SDRCON_PIPE1 ;;
         SDRCON = xr0 ;;

Do other register besides SYSCON and SDRCON, effect the SDRAM controller?

 

thanks,

tim

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