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PLL loop filter

Question asked by qwerty99 on Sep 18, 2014
Latest reply on Sep 19, 2014 by qwerty99

I'm thinking of using an ADF4108 evaluation board for a project. I haven't used a PLL before, but have researched them reasonably well and understand the basics.

 

I have experience with P/PI/PID controllers, so naturally I tend to think about a PLL as just another control system.

 

But one thing puzzles me. Let me explain.

 

A simple loop filter (PI filter) consists of a resistor and capacitor in series, driven from the PFD charge pump. A small capacitor across the CP output is often also present, to give additional filtering at higher frequencies. This all makes sense to me. At sufficiently low frequencies this filter behaves as an integrator, with a phase lag of 90 degrees. No problems so far.

 

The variable that is being controlled is phase, at least when the loop is in lock.

 

The VCO does not, strictly speaking, control phase, but frequency. That is, a change in VCO voltage results in a change in frequency. The VCO gain is expressed in MHz/volt, not in radians per volt. Phase is the time integral of frequency. Therefore, as far as our controlled variable (phase) is concerned, the VCO behaves as an integrator. If you change the VCO voltage, then the phase of the VCO output will ramp linearly with time - that is the classic behaviour of every integrator. Of course, the phase lag (in the VCO output phase) is 90 degrees, just as with every integrator.

 

Therefore, at low frequencies, we have TWO integrators in the control loop, the loop filter and the VCO, and both have a phase lag of 90 degrees, so the total phase lag is 180 degrees. Now, as we know, if the loop gain is greater than or equal to one, at a frequency where the total phase lag is 180 degrees, then the loop will be unstable and oscillate. The gain of both integrators increases with decreasing frequency (as with all integrators), so we can state with certainty that at some sufficiently low frequency, the gain will be greater than one, and the total phase lag equal to 180 degrees, so the loop will be unstable.

 

However, PLL loops are not (usually) unstable, so there must be something wrong with my reasoning. Where is the fault in my reasoning above?

 

Thanks

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