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SPI flash booting : wrong clk idle level

Question asked by QuentinBerthet on Sep 17, 2014
Latest reply on Sep 18, 2014 by QuentinBerthet

Hi everyone,


I am struggling with the SPI boot of a 21489 (custom hardware) on a flash device (M25P16).

(I successfully booted the board in slave mode from a uC, so I am confident that the hardware is fine)


The DSP seems to be clocking the read opcode for the flash correctly, but the flash isn't sending any data back on the MISO line.

The only explanation I have found so far is that the CLK line is not at high level before the start of the boot. The clock toggle to high level at the same time the DSP drive the CS line low, so I guess that the SPI Flash is interpreting this transition as the first clock pulse and so the opcode is shifted by 1 bit and this misinterpreted by the flash.


I have found the following discussion related to this problem:

214xx processors: pull down resistor at SPI_CLK(DPI3) pin may result in SPI master boot failure


But in my case, I DON'T have any pull down on the CLK line. I have tried leaving the line floating or pulling it up to VCC without success.

I disconnected every device on the SPI bus except the DSP and flash, so I don't understand why the clock stay at low level before the boot start.


Have someone seen this situation before ?


Thanks in advance.

Best regards