I have a design with the ADV8005 that is failing the HDMI Clock Duty Cycle Test. The HDMI clock is being driven with a ~35% duty cycle. This is happening when driving 4k30 video.
The input video clock looks good on a scope and is 50% duty cycle. The 27Mhz crystal is also measured at 50% duty cycle.
See attached register dump.
I have tried setting the CCI_CONTROLS (Bit0 of 0xECEA) and this has no effect on the HDMI Clock.
Any information would be appreciated.