AnsweredAssumed Answered

Clock chip selection and Clock level transition!!!???

Question asked by civili on Sep 16, 2014
Latest reply on Sep 16, 2014 by Kyle.Slightom

We are developing precision data acquisition system based on AD7760. But now we are facing some problems on the system clocks distribution.

There are two AD7760s on our board, as we want to capture uV level signal, so the system is very sensitive to the clock jitter. And also our system need synchronize with GPS exactly, so we need to use the clock output from the GPS chip to be the system clock source. The GPS chip can output two time pulses, one is 1PPS, another is any frequency clock 1Hz-10MHz. Now we choose the second timepulse's output as the system clock source, and configure its output to be 8MHz.


After GPS, we should use a clock chip to generate other frequencies to be used for ADCs/FPGA, the frequencies we want to generate are 40MHz, 25.6MHz, etc... And the system clock architecture diagram is attached.

Our problem are:

Is this clock distribution design reasonable?

Now we roughly choose AD9517 as the clock chip. Is it the best choice for this application?

And more confuse to us is, the output level of clock chip is LVPECL/LVDS/LVCMOS. But AD7760 clock input MCLK needs 5V single-end clock level. How to make this level transition???

Thanks in advance!