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[ADuCM361] ADCxFLT register setting

Question asked by sofy Employee on Sep 16, 2014
Latest reply on Sep 18, 2014 by MMA


I would like to ask again about UG-367 page29, Table16 fADC calculation formula.

It seems wrong formula compare with device default value.


ADCxFLT default value is 0x007D after power on.

So it mean ADCxFLT register SF[6:0] = b111 1101 (dec125).

125,000 / ((SF + 1) x 16) = about 62Hz but device output is 50Hz actually.


Also UG-367 page 31 example code "DMA Configration for Moving ADC0 Result Directly to memory" says:

pADI_ADC0 -> FLT = 0x7D;   // 50Hz sampling rate, chop off


So 50Hz seems a correct value, but Table 16 formula doesn't lead this value. (62Hz).


Is it a

125,000 / ((SF + 1) x 16)

on Table 16 typo?


Thank you for your help in advance.

Best regards,