We want to configure adv7611 for 24 bit i2s mode,
We are getting sclk as 3.07 Mhz.
Is it fixed clock generated by ADV7611; so even if data is less it will be filled by zero.
Or it must be only 2.304 MHz,
It is the standard implementation if I2S to have 32 bit clock cycles per channel so 64 BCLK cycles per frame. The 24 bit audio word is usually left justified within the 32 bits leaving 8 zero bits after the audio data. So 64 bits per frame (sample period) will give you 3.072 MHZ for the serial BCLK. So yes, this is normal for 24 bit I2S
3.072 MHz is normal for SCLK.
Are you using one of our evaluation boards for ADV7611 or ADV7612?
We are using a custom board having ADV7611.
We want to configure it for HDMI audio in 24 bit I2S format.
We are getting following timings:
MCLK = 6.14 MHz
SCLK = 3.07 MHz
LRCLK = 48KHz
MCLK and LRCLK are perfect; but SCLK is giving perfect timing for 32 bit.
So Is it normal or it must be 2.304MHz(specific to 24 bit).
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