In basic settings( both lo_freq = 2.4GHz, bw = 18MHz and samp_freq = 30.72MHz),
How can i calculate the time(period) between sample to sample?
The clock itself is running at 4x the sample rate. But the data that you are monitoring is only updated every 4 clock cycles. So the update rate of the data is the sampling rate.
Moved to FPGA Reference Designs.
Well, period = 1/sample_freq.
Is it only affected by samp_freq ?
and is the samp_freq divided by 4 for each clock?
I appreciate for your kind answer.
I want to ask one more simple thing and this would be the last question
The implementable shortest sample period with fmcomms3 is (1/61.44MHz), right?
Yes. The maximum sample frequency is 61.44 MHz. But be aware that the analog bandwidth is limited to 56 MHz.
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