In basic settings( both lo_freq = 2.4GHz, bw = 18MHz and samp_freq = 30.72MHz),

How can i calculate the time(period) between sample to sample?

Moved to FPGA Reference Designs.

Well, period = 1/sample_freq.

- Lars

Thanks, larsc.

Is it only affected by samp_freq ?

and is the samp_freq divided by 4 for each clock?

Hi,

The clock itself is running at 4x the sample rate. But the data that you are monitoring is only updated every 4 clock cycles. So the update rate of the data is the sampling rate.

I appreciate for your kind answer.

I want to ask one more simple thing and this would be the last question

The implementable shortest sample period with fmcomms3 is (1/61.44MHz), right?

(and monitor-able)

Yes. The maximum sample frequency is 61.44 MHz. But be aware that the analog bandwidth is limited to 56 MHz.

Hi,

The clock itself is running at 4x the sample rate. But the data that you are monitoring is only updated every 4 clock cycles. So the update rate of the data is the sampling rate.

- Lars