What is the sweep rate of AD9956 and AD9852?
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Moved this question on the AD9956 and AD9852 to the Direct Digital Synthesis community.
Using the evaluation software to calculate the ramp rate at a given system clock input such as 300 MHz. It can go as low as 0.0133 us.
The rising ramp rate = RSRR (decimal) / 2^16 * SYNC_CLK.
The falling ramp rate = FSRR / 2^16 * SYNC_CLK.
The max system clock is 400MSPS.
The SYNC_CLK = system clock/4
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