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AD9361 TX path delay

Question asked by dinc@coherentlogix.com on Sep 12, 2014
Latest reply on Sep 15, 2014 by tlili

Hi,

Where can I find info on the internal TX path delay, from digital data input  to the TX channel differential output (for example Tx1B)?

I can see there is info on digital Tx block delay calculation in the UG-570. Does the rest of the path have negligible delay?

 

I'm sending some test data (beginning with a synchronization sequence) to AD9361 where the first valid data is beginning with the first TX_FRAME high and capturing it (IQ data) with a spectrum analyzer using an external trigger. When I measure the delay between the trigger signal and the first TX_FRAME high on the scope it's ~1us but when the captured data is analyzed the delay looks like ~30 us (Beginning of the test data starts ~30 us after the first captured IQ pair).

Trying to analyze where this 30 us is coming from. Total digital block delay is ~2.3us.

 

Thank you very much for your help.

 

Regards,

Asli

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