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AD9361 REF_CLK

Question asked by dinc@coherentlogix.com on Sep 11, 2014
Latest reply on Sep 22, 2014 by charlyelkhoury

Hi,

In UG-570, Reference Clock Setup and Operation section there is a condition as 'The level for the clock should be 1.3V p-p maximum..'. what would be the impact if the p-p level is higher than 1.3V? Should it ideally be at 1.3 p-p or higher swings are OK too?

 

Thanks,

Asli

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