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Prefetch Abort with Nested VICs?

Question asked by ThorMJ on Sep 9, 2014
Latest reply on Sep 16, 2014 by MMA

I am using the ADuC706x.s from VIC/NestedVIC/ --

  Timer0 - Half-duplex turnaround timer (3.5 chars; I reset it on every TX, and if it expires, I release the line)

  Timer3 - State Machine (32KHz, 1/3rd second or so)

  UART - 115,200 baud

  ADC 8 KS/s [Trying use FIQ on this so it can preempt everything else]

 

When the system is quiet, it seems to work....

When I put code in to print every 4th ADC sample as hex [in my format, 5 chars/sample, after averaging 4x, so 10KB/s], it works for a little while... then I get a Prefetch Abort, and the LR points to line a nonsense location [7fb54].  Sometimes I get a call to IRQ0FIQ, and the LR points to 263 of ADuC706x.s-

     LDMIA   SP!    ,{R12,LR}

 

I tried (my hacktastic way) of turning off nesting by commenting out lines 321, 340, and 251 (the MSR instructions), but  that didn't help.

I tried to move the ADC to the FIQ, but I'm not convinced it moved; I set FIQEN instead of IRQEN, but it's still calling the IntHndlrTable entry instead of the FIQ_Handler...

 

Questions:

  1. Is there a better way to do this?  I tried what I thought was the right way to use the FIQ on the ADC, but it still called the IntHndlrTable instead of calling the FIQ_Handler... and still I end up in PABORT

  2. What is the right/simple way to disable nesting, yet keep the VIC code as-is (using the tables and such)?

  3. There's no ETM on the 7060, so I can't use semihosting as a higher-bandwidth communication device, right?

  4. How do you debug this?

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